1. Field of the Invention
The present invention relates to a clock signal generation circuit of a delay locked loop type, and more particular, to a clock signal generation circuit of a delay locked loop type in which active elements are formed by using a thin-film deposition technique or a printing technique. The present invention also relates to a display panel module, an image sensor apparatus, and an electronic apparatus.
2. Description of the Related Art
Recently, a higher display resolution has been desired not only for large-sized displays but also for medium- or small-sized displays. Under such circumstances, frequencies of input clock signals and image signals have become higher.
For example, a system display in which functional circuits are provided on a display substrate in a concentrated manner converts serial image signals into parallel image signals so that signal frequencies can be lowered. Thus, the operating margins can be improved.
However, problems regarding circuit delay and operating margins still exist in a circuit portion where parallel conversion of image signals has not yet been performed. In particular, in the case of recent system displays for which the input frequency of an image signal is very high, a delay difference occurring between a clock signal and the image signal on the display substrate causes sampling failure.
Clock signal generation circuits of a delay locked loop type described, for example, in Japanese Unexamined Patent Application Publication Nos. 2006-287641 and 2007-6517 are available.